In a load drive circuit built in a source driver of a liquid crystal display panel and used, for example, when a signal line of the liquid crystal display panel is driven, a phase compensator is built in with an intention of improvement of a phase characteristic, prevention of oscillation of the circuit, and the like (see, for example, Patent Documents 1, 2, and 3).
An example of such a load drive circuit in which the phase compensator is built is shown in FIG. 12. As shown in the figure, this load drive circuit includes an output terminal OUT to which a load (not shown) should be connected, an input terminal IN to which an input signal should be given, a final amplifier AMP0 including output elements (P1 and N1) for driving the load, preamplifiers (AMP1 and AMP2) for driving output elements (P1, N1) included in the final amplifier according to an input signal, and phase compensators (a rising edge phase compensator 13 and a falling edge phase compensator 14) for improving a phase characteristic between input and output signal waveforms and is constituted such that an output signal of a non-inverting form appears at the output terminal according to the input signal given to the input terminal IN.
In this example, the final amplifier AMP0 is constituted by a complementarily-connected pair of output elements (a MOS field effect transistor P1 of a p-channel type (hereinafter simply referred to as “transistor P1”) and a MOS field effect transistor N1 of an n-channel type (hereinafter simply referred to as “transistor N1”) The output elements (the transistors P1 and N1) are biased such that the final amplifier AMP0 performs, for example, a class AB operation.
The preamplifier is constituted by a first inverting amplifier AMP1 that amplifies an electric potential difference between the input terminal IN and the output terminal OUT and gives the electric potential difference to a control input terminal (a gate terminal GP1) of a high-potential side output element (the transistor P1) of the final amplifier AMP0 and a second inverting amplifier AMP2 that amplifies an electric potential difference between the input terminal IN and the output terminal OUT and gives the electric potential difference to a control input terminal (a gate terminal GN1) of a low-potential side output terminal (the transistor N1) of the final amplifier AMP0.
The rising edge phase compensator 13 includes a series circuit of a resistive element R1 and a capacitor C1 inserted between the control input terminal (GP1) of the high-potential side output element (the transistor P1) and the output terminal OUT. The falling edge phase compensator 14 includes a series circuit of a resistive element R2 and a capacitor C2 inserted between the control input terminal (GN1) of the low-potential side output terminal (the transistor N1) and the output terminal OUT.
A waveform chart showing signal waveforms of respective sections of the load drive circuit is shown in FIG. 13. As shown in the figure, when an electric potential of the input terminal IN changes from a low electric potential to a high electric potential, the first inverting amplifier AMP1 reduces the electric potential of the gate terminal GP1 of the transistor P1 and, at the same time, the second inverting amplifier AMP2 reduces the electric potential of the gate terminal GN1 of the transistor N1 such that the electric potential of the output terminal OUT and the electric potential of the input terminal IN become the same electric potential.
Then, a driving ability of the transistor P1 increases because an electric potential difference between a gate and a source increases. On the other hand, a driving ability of the transistor N1 decreases because the electric potential difference between the gate and the source decreases.
At this point, the capacitor C1 included in the phase compensator 13 is instantaneously discharged through capacity division by a load capacitor connected to the output terminal OUT. Thus, the electric potential of the gate terminal GP1 of the transistor P1 is reduced only in a certain period immediately after the rising edge of the input terminal IN and an initial driving ability of the transistor P1 is further intensified. Consequently, the electric potential of the output terminal OUT can instantaneously rise following the electric potential of the input terminal IN and a phase characteristic is improved.
On the other hand, when the electric potential of the input terminal IN changes from a high electric potential to a low electric potential, the first inverting amplifier AMP1 increases the electric potential of the gate terminal GP1 of the transistor P1 and, at the same time, the second inverting amplifier AMP2 increases the electric potential of the gate terminal GN1 of the transistor N1 such that the electric potential of the output terminal OUT and the electric potential of the input terminal IN become the same electric potential.
Then, a driving ability of the transistor P1 decreases because an electric potential difference between the gate and the source decreases. On the other hand, a driving ability of the transistor N1 increases because the electric potential difference between the gate and the source increased.
At this point, the capacitor C2 included in the phase compensator 14 is instantaneously charged through capacity division by a load capacitor connected to the output terminal OUT. Thus, the electric potential of the gate terminal GN1 of the transistor N1 is increased only in a certain period immediately after the falling edge of the input terminal IN and an initial driving ability of the transistor N1 is further intensified. Consequently, the electric potential of the output terminal OUT can instantaneously fall following the electric potential of the input terminal IN and a phase characteristic is improved.
Patent Document 1: Japanese Patent Laid-Open No. 6-216662
Patent Document 2: Japanese Patent Laid-Open No. 7-106871
Patent Document 3: Japanese Patent Laid-Open No. 11-249625